1. Field of the Invention
The present invention relates to a metal-insulator-metal capacitor and a method of fabricating same and, more particularly, to a metal-insulator-metal capacitor incorporating metal studs or vias to increase the density thereof and reduce manufacturing costs, and a method of fabricating same.
2. Description of the Related Art
Contemporary integrated circuit design demands large capacitors having high density to meet the needs of higher density integrated circuits. Capacitors may be used for a number of functions, including, for example, as a reservoir capacitor for a charge pump circuit or for noise decoupling.
Some known high density capacitors use a metal-insulator-metal (MIM) structure. MIM capacitors are valuable components in memory, logic and analog circuits. Some MIM capacitors are bulky planar devices introduced into integrated circuits at the back-end-of-line (BEOL) and require dielectric materials with low processing temperatures. The dielectric materials may include SiO2 or Si3N4 deposited using plasma enhanced chemical vapor deposition (PECVD) and have capacitance densities ranging from about 1 to 1.5 fF/μm2. These capacitors, referred to as horizontal plate capacitors, demand large chip area. U.S. Pat. No. 5,926,359 to Greco et al., for example, relates to a known horizontal plate capacitor.
The ongoing scaling of very large scale integration (VLSI) circuits requires a reduction of the planar area allocated to an MIM capacitor while maintaining the capacitance requirements. Thickness scaling of current materials has resulted in problems such as increases in leakage current and voltage linearity, and a reduction in lifetime reliability of thinner films.
Building capacitors in the vertical direction is a known method of reducing the amount of chip area occupied by a capacitor. For example, a capacitor may be formed on the sidewalls and the bottom of a deep trench structure. See, e.g., U.S. Pat. No. 6,358,837 to Miller et al. According to known methods, the trenches are formed at the BEOL due to requirements of low temperature metal processing to avoid melting of the electrodes. However, in some instances, it has been suggested to form deep trenches in a silicon substrate and to form the electrodes with doped polysilicon or a metal having a high melting point, such as tungsten. A problem with the use of deep trenches is high processing costs.
As an alternative to deep trenches, another vertical MIM capacitor utilizing a shallow trench structure, has been proposed. See, e.g., U.S. Pat. No. 6,329,234 to Ma et al. The shallow trench is formed by etching insulating material in the BEOL. Capacitors formed in the shallow trench structure have been referred to as semi-interdigitated MIM capacitors. A problem with the semi-interdigitated MIM capacitor is that the surface efficiency may be only 50–60%, which means that the semi-interdigitated MIM capacitor does not allow all the nodes to couple at all surfaces.
Reduction in available area has also led to the introduction of alternative high dielectric constant materials such as Al2O3, Ta2O5, HfO2 and laminate stacks thereof. See Hu, H., IEEE Elect. Dev. Lett., Vol. 23, No. 9, 2002. The introduction of the alternative materials may require integration processing, such as reactive ion etching (RIE) to pattern the MIM capacitor area. In some cases, the RIE patterning of the alternative materials requires plasma etching at elevated temperatures and/or a dual step process of plasma etching followed by a wet chemical etch. Such processing required when using the alternative materials increases manufacturing costs. For example, HfO2 is a material that is difficult to etch. See Sematech, “FEP Surface Preparation”, Monthly Report, December, 2002.
Therefore, there exists a need for a low-cost MIM capacitor and method of fabricating same, which can increase capacitor density and utilize some of the existing semiconductor processing steps so as to reduce integration cost.